The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing an isolation structure for use in isolating III-V compound semiconductor field effect transistors (FETs), and a method of forming such a semiconductor structure.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits.
Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical. In some applications, improved performance can be achieved by replacing a silicon channel with a high carrier mobility semiconductor material. One promising class of high carrier mobility semiconductor materials that have received considerable interest as a replacement semiconductor material for silicon is III-V compound semiconductor materials.
Although III-V compound semiconductor based FETs can achieve a higher performance than their silicon counterparts, a problem exists in forming an isolation structure using III-V compound semiconductors. Notably, the processes used to form isolation structures employed in silicon based technologies are not compatible with III-V based semiconductor devices. For example, field oxide isolation structures are formed using a high temperature oxidation process which cannot be performed with III-V compound semiconductors. Moreover, shallow trench isolation structures require the use of a chemical mechanical planarization (CMP) process which is presently difficult to perform with III-V compound semiconductors. Mesa isolation structures are also possible but such isolation structures require the use of semiconductor-on-insulator substrates or semi-insulator materials, and cannot be performed using doped semiconductors.
In view of the above, there is a need for providing a semiconductor structure containing an isolation structure for use in isolating III-V compound semiconductor FETs that avoids the problems and drawbacks associated with using existing isolation structures.